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Difference between module and class based testbench
Difference between module and class based testbench









difference between module and class based testbench

Each phase is defined by its own virtual method, which derived components can override to incorporate component-specific behavior. UVM Components execute their behavior in strictly ordered, pre-defined phases. We will discuss about phasing concept in this section and rest of the features will be discussed as separate topics. Uvm_compoenent class is inherited from uvm_report_object which is inherited from uvm_object.Īs I mentioned previously, uvm_component class provides features like hierarchy searching, phasing, configuration, reporting, factory and transaction recording. If the agent is passive, subtypes should contain only the monitor. If the agent is active, subtypes should contain all three subcomponents. NOTE: uvm_env and uvm_test are also extended from uvm_component.Īn agent typically contains three subcomponents: a driver, sequencer, and monitor. Uvm verification component classes are derived from uvm_component class which provides features like hierarchy searching, phasing, configuration, reporting, factory and transaction recording.įollowing are some of the uvm component classes As there is no difference between uvm_env and uvm_component, we will discuss about uvm_component, in the next section. A environment class can also be used as sub-environment in another environment. uvm_env is used to create and connect the uvm_components like driver, monitors, sequeners etc. Uvm_env is extended from uvm_component and does not contain any extra functionality. Uvm components, uvm env and uvm test are the three main building blocks of a testbench in uvm based verification.











Difference between module and class based testbench